Cognichip closed a $60 million round aimed at building AI-native tools for semiconductor design. The target is one of the oldest, slowest and most expensive workflows in technology: the multi-year, billion-dollar cycle that turns a chip architecture into a tapeout.
Existing EDA software — Synopsys, Cadence, Siemens — is the incumbency Cognichip is attacking. These tools are astonishingly deep but were architected in an era before foundation models. Cognichip's pitch is that placement, routing, verification and even architectural trade-off exploration are tasks where domain-tuned models can deliver results in hours that currently take teams weeks.
If the claims are real, the economic effect extends well past Cognichip's revenue. Compressing the design cycle even modestly reduces the cost of building a custom AI accelerator, which in turn widens the pool of companies that can credibly design their own silicon. That is a meaningful shift in how power is distributed in the chip industry — today the design tooling is a chokepoint almost as structural as TSMC's fabs.